The importance of CMOS technology in the VLSI field has grown, as a result of requirements for a high noise margin and low power consumption. However as miniaturization has increased, serious problems have arisen with regard to preventing stray thyristor operation which causes the CMOS latch-up phenomenon to occur between mutually adjacent portions of an n-channel MOSFET and p-channel MOSFET, and with regard to maintaining a sufficient level of withstanding voltage between mutually adjacent elements.
Various forms of device configuration and manufacturing process have been proposed for overcoming these problems. These proposals include the use of a configuration containing wells, formation of a buried high concentration layer, and formation of a self-aligned channel stop at the edge of a well region.
Summaries of these various structures and methods will be given successively in the following, together with respective problems that have arisen with these.
Firstly, a method which uses an epitaxial structure over a high dopant concentration substrate will be described, referring to FIG. 17. This structure has been proposed by Yuan Taur et al, in the I.E.E.E. Transactions on Electron. Devices, Vol. ED-32, No. 2, February 1985 pp. 203-209.
In FIG. 17 numeral 51 denotes an n-type well, 52 is a high dopant concentration substrate (p.sup.+), 53 denotes a low dopant concentration epitaxial layer (p), 56 denotes an insulating isolation layer, 60 denotes a channel stop (p.sup.+). The region PA in the left half of the diagram is a p-channel transistor region, and region NPA in the right half of the diagram is an n-channel transistor region.
With this structure, a thin epitaxial layer 53 having a thickness of 4.5 .mu.m is formed upon the high concentration (at least 10.sup.19 cm.sup.-3) substrate 52, and then a 2.5 .mu.m layer of photoresist is selectively formed. Using the photoresist layer as a mask, high-energy implantation of phosphorus at 700 KeV is performed, and then short-term annealing for 4 hours at 1050.degree. C. is executed. As a result, a retrograde n-well 51 is formed, having a peak value of concentration in a deep portion of the well. Due to the formation of this n-type well 51 by high-energy implantation, and low-temperature short-term annealing, diffusion of boron (i.e. the substrate dopant) from the high concentration substrate 52 is prevented, and it becomes possible to form the n-type well 51 in the thin epitaxial layer 53, to thereby enhance the CMOS latch-up prevention capability.
Normally with such a semiconductor device structure, the high concentration substrate (p.sup.+) 52 is connected to ground potential (Vss) while the n-type well 51 is set to the power supply potential (V.sub.DD) due to the n.sup.+ layer 54 (provided for fixing the potential of the well) that is disposed closely adjacent to the source region 55s of the p-channel transistor.
A stray vertical pnp transistor arises with this structure, where p, n and p thereof are respectively the drain region 55d of the p-channel transistor, the n-type well 51, and the low dopant concentration epitaxial layer (p) 53 together with the high concentration substrate (p.sup.+) 52. If for example latch-up trigger current flows (as holes h injected from the drain region 55d) to pass through the virtual base region (i.e. the n-type well 51) and enters the low dopant concentration epitaxial layer 53, then this current will be immediately absorbed by the high concentration substrate (p.sup.+) 52 which is securely held at a fixed potential at its rear face. This serves to prevent any localized increase in potential of the low dopant concentration epitaxial layer 53. A stray lateral npn transistor also arises, having the low dopant concentration epitaxial layer 53 as its virtual base. The n, p and n of this stray lateral npn transistor are respectively the drain region 54d of the n-channel transistor, the low dopant concentration substrate (p) 53, and the n-well 51. However due to the device structure, this stray transistor cannot be set in the ON state. Thus with this configuration, a sufficient degree of suppression of the stray vertical pnp transistor operation is achieved, to thereby suppress latch-up.
However as described hereinafter, a stray lateral pnp transistor is formed below the insulating isolation layer 56, (where the p, n and p of this transistor are respectively the drain region 55d of the p-channel transistor, the well 51, and the low dopant concentration epitaxial layer (p) 53), and this in conjunction with the stray lateral npn transistor (where n is the drain region 54d of the n-channel transistor, p is the low dopant concentration substrate (p) 53, and n is the n-type well 51) forms a stray PNPN thyristor. As the structure is increasingly miniaturized, the width of the insulating isolation layer 56 becomes so small that satisfactory performance cannot be achieved, due to the presence of this stray PNPN thyristor.
For that reason, to suppress CMOS latch-up with this technology, it is necessary to limit the minimum spacing between the n-channel transistor and p-channel transistor to approximately 4 .mu.m. If the spacing is further reduced, then the epitaxial layer 53 must be made even more thin. However it is necessary to suppress the diffusion of boron (i.e. the substrate dopant) from the high concentration substrate 52 to an absolute minimum. This is very difficult to achieve. The problem of reducing the spacing width of the insulating isolation layer 56 is closely related to the method of forming the n-type well 51, and the configuration and method of forming the channel stop 60 which is disposed immediately below the insulating isolation layer. The basic features of forming the n-well 51 and the channel stop 60 will be described referring to FIG. 18.
Firstly, an oxide film 82 and a nitride film 81 are formed on the surface of the low dopant concentration epitaxial layer 53, which has been grown upon a high concentration substrate (p.sup.+) 52. A photoresist pattern 83 is then selectively formed on the result, and ion implantation of the n-type well 51 is executed through this pattern. An insulating film 84 is then formed over the entire surface (FIG. 18(a)).
Next, lift-off processing is executed such that the insulating film 84 is left only upon the region of the n-well 51. Further patterning processing is then executed to form a photoresist pattern that corresponds to the insulating isolation layer 56. The channel stop 60 is then formed by implantation (FIG. 18(b). It is important to note that the channel stop 60 is formed by means of the insulating film 84 such as to substantially coincide in position with the edge of the n-type well 51. That is to say, with this process, the channel stop 60 is formed at the edge of that n-type well in a substantially self-aligned manner.
Using the photoresist pattern 85, etching of the insulating film 84 and the nitride film 81 is executed, and a nitride film pattern is formed corresponding to the insulating isolation layer 56 (FIG. 18(c)). Next, the insulating isolation layer 56 is formed by the usual LOCOS thermal oxidation process (FIG. 18(d).
A very important question with regard to this process is that at the point in time at which ion implantation is executed of the channel stop 60 (which generally has a higher concentration than the n-type well 51), the region of the n-type well 51 has been compensated by migration in the lateral direction. In addition, as a reult of the thermal oxidation processing of the portion 161 (shown in FIG. 18(d)) of the channel stop 60, large-scale diffusion occurs within the n-type well 51, due to the effect of oxidation-enhanced diffusion. Due to this diffusion, part of the n-type well dopant ions are compensated in a localized region, whereby reduction of the width of the virtual base region (n-well 51) of the stray lateral pnp transistor occurs ((where the P, N and P of this transistor are respectively the drain region 55d of the p-channel transistor, the n-well 51, and the low dopant concentration epitaxial layer (p) 53). The h.sub.FE of this stray pnp transistor is thereby increased, and that transistor therefore responds very sensitively to injection of a trigger current from the drain region 55d of the p-channel transistor. This is a serious defect, which results from reduction of the size of the insulating isolation layer 56, i.e. which is caused by an increased degree of miniaturization.
Another proposal has been made by K. W. Terril et al, (I.E.E.E. 1984 I.E.D.M) Technical Digest pp. 406-409, which is shown in FIG. 19. In FIG. 19, numeral 61 denotes an n-well, 62 is a high concentration buried layer (p.sup.+), and 63 denotes a low dopant concentration substrate (p).
With this structure, after the n-well 61 has been formed, the high concentration buried layer (p.sup.+) 62 is formed uniformly at a location which is deeper than the n-well 61. In the same way as for the epitaxial structure described above, a stray pnp transistor arises (where p is the drain region 65d of the p-channel transistor, n is the n-well 61, and p is the low dopant concentration substrate (p) 63 and the high concentration buried layer (p.sup.+) 62). If a latch-up trigger current flows from the drain region 65d for example, due to the injection of holes h, the structure has the objective of suppressing any localized increase in potential which might result from this current passing through the virtual base region (i.e. the n-well 61) into the low dopant concentration substrate 63.
However this structure differs from the epitaxial structure example in that the potential of the high concentration buried layer (p.sup.+) 62 is floating, and hence such a trigger current cannot be absorbed with sufficient effectiveness, as is achieved with the epitaxial structure.
In addition, both with the structure using the epitaxial layer and the structure in which a high concentration region is formed by implantation, similar problems occur. That is to say, of the holes that pass into the low dopant concentration substrate through the n-well (having been injected from the source or the drain region of the p-channel transistor), most will be absorbed by the high concentration region. However those holes which flow in the lateral direction will not be absorbed sufficiently, and this will result in the potential of a specific region of the low dopant concentration substrate being increased. Hence, a trigger current will flow through that portion, which will turn on the stray PNPN thyristor, and hence will result in the latch-up phenomenon occurring. This is a very serious problem, that results from a reduction in the spacing between the borders of the n.sup.+ and p.sup.+ layers of the regions that constitute the complementary transistor pair, and presents an obstacle to increased levels of integration of CMOS complementary semiconductor devices.
In addition, in the case of the epitaxial structure, the cost of an epitaxial wafer is high, and it is difficult to attain increased productivity by achieving stable manufacture of large-diameter wafers having a thin epitaxial layer. Furthermore it is necessary to make the thickness of the epitaxial region (i.e. the low dopant concentration region) as small as possible, in order to assure effective absorption of holes. However a problem arises that a very shallow low dopant concentration region cannot be achieved, due to out-diffusion (i.e. diffusion of substrate dopant ions) from the high concentration region during growth of the epitaxial layer. On the other hand with the method in which a high concentration region is formed by implantation, although the manufacturing cost is not excessive, it is not possible to achieve a sufficient degree of effectiveness of suppression of the CMOS latch-up phenomenon, since it is not possible to fixedly determine the potential of the high concentration buried layer (p.sup.+) at its rear face or by a diffusion layer formed on the upper face of the semiconductor substrate. In order to increase the dopant concentration of the high concentration buried layer (p.sup.+), to achieve sufficient absorption of the trigger current, it is necessary to use high-energy high-dose implantation (1.0.times.10.sup.14 cm.sup.-2 or higher). However the problem then arises that point defects are produced within the substrate.
Thus, with both the epitaxial structure and the structure having a high concentration buried layer formed by high-energy high-dose implantation, satisfactory characteristics cannot be achieved.
Another example of the use of a well and of a channel stop below the insulating isolation layer in a miniaturized device will be described referring to the manufacturing process cross-sectional views of FIG. 20. This has been proposed by R. A. Martin, (I.E.E.E. 1984 I.E.D.M) Technical Digest pp. 403-406.
With this manufacturing process, a channel stop is formed directly below an insulating isolation layer, between mutually adjacent portions of the n-channel and p-channel transistors. The objective of the proposal is to achieve simplification of the manufacturing process and a more miniaturized structure.
In FIG. 20(a), firstly a p-type dopant is implanted to a high concentration, to form an n-channel stop 75, in a portion of a region which will constitute an insulating isolation layer. Next, an insulating isolation layer 76 is formed by the usual LOCOS thermal oxidation processing, and then a pattern of photoresist 80 is formed over a part of the insulating isolation layer 76. At this time, the n-type channel stop has been diffused into the interior of the substrate as a result of the aforementioned thermal oxidation (FIG. 20(b)).
Next, in FIG. 20(c), high-energy n-type implantation is then executed through the photoresist pattern 80, to produce a comparatively high concentration n.sup.+ region as an n-well 71, together with a high concentration n.sup.+ region that is disposed immediately below a portion of the insulating isolation layer 76 and constitutes a part of the n-well 71. Thus, a p-type channel stop is formed in a single step.
Using the normal manufacturing process, a gate oxide film 78, gate electrode 77, and source and drain regions 73s, 73d and 74s, 74d and aluminum connecting lead 79n are then formed, to obtain a complementary semiconductor device as shown in FIG. 20(d).
Thus with this manufacturing process, the p-type channel stop is formed by a compensation method through implantation of n.sup.+ ions, executed in a condition in which p.sup.+ diffusion to form an n-type channel stop has already occurred. In this way, oxide-enhanced diffusion of the type shown in FIG. 18 will not cause diffusion into the n-well from the channel stop 75. However it is extremely difficult to set the dopant concentration for the channel stop at the n-type well 75 side, to achieve correct compensation. That is to say, the concentration is established by implantation processing, and the p.sup.+ channel stop 75 is also affected by oxide-enhanced diffusion resulting from the LOCOS processing. It is necessary to control the n.sup.+ implantation precisely, and in addition to accurately control the concentration distribution in the depth direction, such as to obtain both of the requisite concentrations for the p.sup.+ channel stop 75. If there is even a small amount of inaccuracy, then the shape of the boundary portion 176 shown in the drawings will not be accurately determined, so that the threshold voltage Vt at the n-well 71 side of the insulating isolation layer 76 will be lowered, and hence the channel stop function will not be achieved. Furthermore, this method of manufacture raises particular problems with regard to the n-type channel stop 75, which is not compensated. That is to say, due to the work function of the connecting leads (formed of n.sup. + polysilicon or Al) which are formed on the insulating isolation layer 76, the threshold voltage of the stray n-channel MOSFET can easily become lower than the threshold voltage of the stray p-channel MOSFET. In order to increase the threshold voltage of the stray n-channel MOSFET it is necessary that the n-type channel stop 75 have a high dopant concentration. However due to the fact that the p-type channel stop is formed by compensation, the concentration of the n-type channel stop 75 will only be a fraction of that of the p-type channel stop. Thus it is difficult to set the level of concentration of the n-type channel stop 75 to a sufficiently high value. For these reasons, the width of the insulating isolation layer cannot, be reduced by very much.
Furthermore, due to the fact that the n.sup.+ implantation forms the n-well 71 at the same time as the channel stop is formed, in order to simplify the processing, a CMOS structure providing optimum suppression of latch-up cannot be achieved, since the optimum implantation conditions for forming the channel stop and the optimum implantation conditions for forming the n-well 71 do not coincide. Thus this method is not suitable for obtaining increased miniaturization.
As described above, the prior art proposals can be broadly divided into two types, i.e. a structure and method of manufacture in which a high concentration layer is used for suppression of the stray vertical transistor effect, and a structure and method of manufacture in which a channel stop is provided below the insulating isolation layer, for suppressing the stray lateral transistor effect.